Playing with the Cyclone V SoC system – DE0-Nano-SoC Kit/Atlas-SoC

Recently I bought the DE0-Nano-SoC Kit/Atlas-SoC development board from Terasic which contains a Cyclone V SoC from Altera.
The board is a good starting point to get involved in embedded system development with SoCs.
The Cyclone V SoC is a FPGA combined with a dual-core ARM® Cortex®-A9 hard processor system (HPS) and some peripherals.

The test system which was designed is meant as a starting point for further designs, and to explore the possibilities of the Cyclone V SoC system.

The design demonstrates:

  • HPS-to-FPGA bridge
  • lightweight HPS-to-FPGA bridge
  • Control of LED via HPS-to-FPGA bridge
  • Hardware accelerated calculations outside the HPS
  • On chip RAM
  • DMA controller transfer RAM to RAM and RAM to GPIO
  • Scattering Gather DMA controller DDR-RAM to GPIO
  • Clock crossing bridge
  • Reserve a dedicated amount of the DDR-RAM for Linux and the FPGA
  • The whole description can be found under Playing with the Cyclone V SoC system – DE0-Nano-SoC Kit/Atlas-SoC

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    3 comments on “Playing with the Cyclone V SoC system – DE0-Nano-SoC Kit/Atlas-SoC
    1. crmann says:

      Really helpful information! This is the best example / tutorial for the HPS-FPGA interface I’ve seen to date. One note: I ran into an issue compiling the Qsys design, as the “intr_capturer” IP was missing from the IP folder (this is found in the original GHRD source). I’m not sure if this was intentional, but wanted to pass that along. Other than that, the design example worked perfectly – thanks again for offering such a great reference design!

    2. Robin says:

      Keep in mind that if you plan to use these (by all means, great tutorial!) to move large amounts of data at once, you have to change the type of writelength to uint32_t instead of uint16_t.

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